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F Jhis )o J %hOvP`J&LB F*F #pY%@F5J@ 1F5 (J J FC A @ GC Injection: SubBlock UTC_ATCL2_CACHE_4K_BANK, Instance %s -C(F 0 $IF hs o I % h F J(J OvJhJ&1FȱHHB F*F # (Y%@FJ1F5 (J FC A x@ GC Injection: SubBlock UTC_VML2_BANK_CACHE, Instance %s -C(F 0 $IF hs o I % h F (J OvJhJ&1F2ȱH lB F*F # (Y%@FGJ1F5 (J FC 𢸼A @ @ @
@ J@ i@ @ @ @ @ GC Injection: SubBlock UTC_VML2_WALKER, Instance %s -C(F 0 $IF hs o I % h F R(J OvJhJ&1FȱHHB F*F #( (Y%@FJ1F5 (J FC A p@ GC Injection: SubBlock UTCL2_ROUTER, Instance %s p8( J!^J ( !F @&JJJ< J8 !DFJ ) !p pG 1F !J%as
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O@!O AO !OhO %; O 3!O8 -OyŲ(Oa@%O`i!O@Q 5OIO15O`9O@!EO O@UO` O@q eOiO ! ' &< '2!8'-OwƲ(Oa@&O`g!O@Q 6OGO16O`7O@!FO O@VO`O@q fOgO !O %H@H@)FȱH@1FH@AFhH@IF8H@9F %J F (F F@F (?ѤD)
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!*3A @ GC Injection: SubBlock UTCL2_ROUTER, Instance %s LF F Q@1 F @ 8( J!J ( !F @JJJ@ J8 !FJ ) FF !@ FF !@ FF !~@ FF !s@ |L Ozv. F)F>| -AFF FF !"FJJ`)@CC F ( '8F-AFF FF !"F)J`)@CC F ( '8F HL !"FJ !"F@C (J ;L !"FJ !"F@C (J @L !"FJ !"F@C (J -A L &@x@w !"F+FhFEO 8 B6?ܽ -AL &@x@w !"F+FhFEO 8 B6?ܽ -AL &@x@w !"F+FrhFEO 8 B6?ܽ JF p ! SJ @@B p L -O '(gN
FFF $0xB !CFEh *F( (O!*F !4 (Bă"MO O pxEX)@ !;F "FP!"F ( 'L F`p !0t ! 'J8F -OF O1 JL F O
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UPF 60F > @PF0F 0#0J/'Od40F9F< FPFAF0FIF / xF @ H A program_patrol_scrubber failed. -O4M
FFO &(xB# !SFGh :F (F, ,CC !:F{6 (/x
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FFF $0xB !CFEh *F (O!*F 4 (Bă"MO O pxEX)@ !;F "FrP!"F l ( 'L A F<`p !60t ! '/J8F -OF O1 JL F O
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`xE(U*p !3F:F ( ~@ 3лєI@@ !:F
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UPFN 60FI > @PFB0F> 00J/'Od40F9F"< qFPFAF 0FIF / xF @ A program_patrol_scrubber failed. -O4M
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J ,B!@=?J J P Љ P Y ,,iF F%,, F",, F">J LQ ! " x I((J pG(J pG( pG1 `J pG A F $_-P%@ !"F M (Ё(( pcs_get_current_state_mi200 xp x 0PCS HIST REG = 0x%X
F $-@<4H - !"FJ !"F@ (J pcs_ras_prbs_error_inject_now_mi100 <F %,HP$P !*FJ ,O@HP$ " y (J pcs_ras_prbs_error_inject_now_mi200 @ ELF F5 - @ F. -O '(iFF & B[&P !#F*F( (O!*F !6 (B%M%NO O EU)@ !;F "FP!"F ( 'L F`p !0t ! 'J8F@ A p( p M $ N(xBV$ ! #4 (J p4A A -OFFF 'x'O e$mFH 0F !:F+F (< (J J p -J . T Yv sH % hH 9u @\5/%kF !*FD (@ @SJ oH % xVH 9u @\5/%kF !*F! (cH*F A ! (WPF8O % MAH 9u @\5/%kF !*FȻ @s<@H % 02H 9u @\5/%kF !*F @c 0H % $H 9u @\5/%kF !*FJ @ c !*F (J program_ras_error_injection_pcs_mi100 pcs_wait_for_mission_mode_mi100 x pcs_get_current_state_mi100 W@ (@ @ pcs_ras_inject_data_parity_error_mi100 @ FdFFle' F(( ? (J A,J , S Xm (`Q J bH % a,`HP$PkF !*F (m @SoJ dH % H,SHP$PkF !*F (T\H, A JHP$ "! (C FI F@CD % ,=HP$PkF !*FH @s+8H % ,3HP$PkF !*F @c-H % ,(HP$PkF !*FJ @ c , HP$ "! (J program_ras_error_injection_pcs_mi200 pcs_wait_for_mission_mode_mi200 @ @ @ @ pcs_ras_inject_data_parity_error_mi200 [@ -OF ZO1 JyL F O pJ O1 (J F O % BW%` !#F2F (!2F ` 5 (N 'O E'V+@ !+F"F ( ~@ 3йыI@@ !"F (К?M t F ( Fj (p F{ ({@1F`E FAr (lOzu F9Fb (b= FZ (T
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@HD<,@DHLP $ X\`dhlpt0reg read -> block_id = 0x%X, operation = 0x%X, address = 0x%X, value = 0x%X, asd_ret = 0x%X reg write -> block_id = 0x%X, operation = 0x%X, address = 0x%X, value = 0x%X, asd_ret = 0x%X reg read 64b -> block_id = 0x%X, operation = 0x%X, address = 0x%llX, value = 0x%X, asd_ret = 0x%X reg write 64b -> block_id = 0x%X, operation = 0x%X, address = 0x%llX, value = 0x%X, asd_ret = 0x%X reg read -> operation = 0x%X, address = 0x%X, value = 0x%X, sys_drv_ret = 0x%X reg write -> operation = 0x%X, address = 0x%X, value = 0x%X, sys_drv_ret = 0x%X reg read 64b -> operation = 0x%X, address = 0x%X, value = 0x%llX, sys_drv_ret = 0x%X reg write 64b -> operation = 0x%X, address = 0x%X, value = 0x%llX, sys_drv_ret = 0x%X pcs_ras_inject_dataloss_error_mi100 pcs_ras_inject_reply_buf_underflow_error_mi100 pcs_ras_inject_elastic_buf_overflow_error_mi100 pcs_ras_inject_reply_buf_overflow_error_mi100 Sucessfully programmed SDMA 4.4 error injection on instance (%d) subblock (%d) UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10 UTC_VML2_IFIFO_GROUP10 GFX_TCX_GROUP10 UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20 UTC_VML2_IFIFO_GROUP20 UTC_VML2_CACHE_PDE0_MEM0 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0 UTC_VML2_CACHE_PDE1_MEM0 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0 UTC_VML2_CACHE_PDE2_MEM0 UTC_VML2_BANK_CACHE_0_4K_MEM0 UTC_VML2_BANK_CACHE_1_4K_MEM0 UTC_VML2_BANK_CACHE_2_4K_MEM0 UTC_VML2_BANK_CACHE_3_4K_MEM0 UTC_VML2_BANK_CACHE_0_BIGK_MEM0 UTC_VML2_BANK_CACHE_1_BIGK_MEM0 UTC_VML2_BANK_CACHE_2_BIGK_MEM0 UTC_VML2_BANK_CACHE_3_BIGK_MEM0 GFX_TCP_UTCL1_LFIFO0 UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0 UTC_VML2_IFIFO_GROUP0 GFX_TCX_GROUP0 GFX_TCC_CACHE_DATA_BANK_0_0 GFX_TCC_CACHE_DATA_BANK_1_0 GFX_TCC_CACHE_DIRTY_BANK_0 UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11 UTC_VML2_IFIFO_GROUP11 GFX_TCX_GROUP11 UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21 UTC_VML2_IFIFO_GROUP21 GFX_CPC_ME1_DC_CSINVOC1 UTC_VML2_CACHE_PDE0_MEM1 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1 UTC_VML2_CACHE_PDE1_MEM1 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1 UTC_VML2_CACHE_PDE2_MEM1 UTC_VML2_BANK_CACHE_0_4K_MEM1 UTC_VML2_BANK_CACHE_1_4K_MEM1 UTC_VML2_BANK_CACHE_2_4K_MEM1 UTC_VML2_BANK_CACHE_3_4K_MEM1 UTC_VML2_BANK_CACHE_0_BIGK_MEM1 UTC_VML2_BANK_CACHE_1_BIGK_MEM1 UTC_VML2_BANK_CACHE_2_BIGK_MEM1 UTC_VML2_BANK_CACHE_3_BIGK_MEM1 GFX_TCP_UTCL1_LFIFO1 UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1 UTC_VML2_IFIFO_GROUP1 GFX_TCX_GROUP1 GFX_TCC_CACHE_DATA_BANK_0_1 GFX_TCC_CACHE_DATA_BANK_1_1 GFX_TCC_CACHE_DIRTY_BANK_1 UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12 UTC_VML2_IFIFO_GROUP12 GFX_TCX_GROUP12 UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22 UTC_VML2_IFIFO_GROUP22 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2 UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2 UTC_VML2_IFIFO_GROUP2 GFX_TCX_GROUP2 GFX_TCC_CACHE_DATA_BANK_0_2 GFX_TCC_CACHE_DATA_BANK_1_2 UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13 UTC_VML2_IFIFO_GROUP13 GFX_TCX_GROUP13 UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23 UTC_VML2_IFIFO_GROUP23 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3 UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3 UTC_VML2_IFIFO_GROUP3 GFX_TCX_GROUP3 GFX_TCC_CACHE_DATA_BANK_0_3 GFX_TCC_CACHE_DATA_BANK_1_3 UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14 UTC_VML2_IFIFO_GROUP14 GFX_TCX_GROUP14 UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24 UTC_VML2_IFIFO_GROUP24 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4 UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4 UTC_VML2_IFIFO_GROUP4 GFX_TCX_GROUP4 UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15 UTC_VML2_IFIFO_GROUP15 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5 UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5 UTC_VML2_IFIFO_GROUP5 GFX_TCX_GROUP5 UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16 UTC_VML2_IFIFO_GROUP16 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6 UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6 UTC_VML2_IFIFO_GROUP6 GFX_TCX_GROUP6 UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17 UTC_VML2_IFIFO_GROUP17 UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7 UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7 UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7 UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7 UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7 UTC_VML2_IFIFO_GROUP7 GFX_TCX_GROUP7 UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18 UTC_VML2_IFIFO_GROUP18 UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8 UTC_VML2_IFIFO_GROUP8 GFX_TCX_GROUP8 UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19 UTC_VML2_IFIFO_GROUP19 UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9 UTC_VML2_IFIFO_GROUP9 GFX_TCX_GROUP9 GFX_TCC_RETURN_DATA GFX_TCC_IN_USE_DEC GFX_CPC_ME1_DC_CSINVOC GFX_CPC_ME2_DC_CSINVOC GFX_TCC_WRITE_CACHE_READ GFX_SQ_LDS_D GFX_CPC_UCODE UTC_VML2_BANK_CACHE GFX_CPC_ME1_DC_RESTORE GFX_CPC_ME2_DC_RESTORE GFX_CPC_ME1_DC_STATE GFX_CPC_ME2_DC_STATE GFX_GDS_INPUT_QUEUE GFX_SQC_DATA_CU0_WRITE_DATA_BUF GFX_SQC_DATA_CU1_WRITE_DATA_BUF GFX_SQC_DATA_CU2_WRITE_DATA_BUF GFX_SQC_DATA_CU3_WRITE_DATA_BUF GFX_TCC_HIGH_RATE_TAG GFX_TCC_LOW_RATE_TAG GFX_CPF_TCIU_TAG GFX_CPC_SCRATCH GFX_TA_FS_AFIFO_HI GFX_TD_SS_FIFO_HI GFX_SQ_LDS_I UTC_ATCL2_CACHE_4K_BANK UTC_ATCL2_CACHE_2M_BANK GFX_TCC_RETURN_CONTROL GFX_RLC_SRM_DATA_RAM GFX_TCP_DB_RAM GFX_TCP_CACHE_RAM GFX_TCI_WRITE_RAM GFX_RLC_TCTAG_RAM GFX_SQC_BANKA_DATA_TAG_RAM GFX_SQC_BANKB_DATA_TAG_RAM GFX_SQC_BANKA_INST_TAG_RAM GFX_SQC_BANKB_INST_TAG_RAM GFX_RLC_SPM_SE0_SCRATCH_RAM GFX_RLC_SPM_SE1_SCRATCH_RAM GFX_RLC_SPM_SE2_SCRATCH_RAM GFX_RLC_SPM_SE3_SCRATCH_RAM GFX_RLC_SPM_SE4_SCRATCH_RAM GFX_RLC_SPM_SE5_SCRATCH_RAM GFX_RLC_SPM_SE6_SCRATCH_RAM GFX_RLC_SPM_SE7_SCRATCH_RAM GFX_RLCG_SCRATCH_RAM GFX_RLC_SPM_SCRATCH_RAM GFX_RLCV_SCRATCH_RAM GFX_SQC_BANKA_DATA_BANK_RAM GFX_SQC_BANKB_DATA_BANK_RAM GFX_SQC_BANKA_INST_BANK_RAM GFX_SQC_BANKB_INST_BANK_RAM GFX_TCP_LFIFO_RAM GFX_RLC_SRM_ADDR_RAM GFX_RLCG_INSTR_RAM GFX_RLCV_INSTR_RAM GFX_SQC_BANKA_DATA_DIRTY_BIT_RAM GFX_SQC_BANKB_DATA_DIRTY_BIT_RAM GFX_TCC_LATENCY_FIFO_NEXT_RAM GFX_EA_MAM_A0MEM GFX_EA_MAM_D0MEM GFX_EA_MAM_A1MEM GFX_EA_MAM_D1MEM GFX_EA_MAM_A2MEM GFX_EA_MAM_D2MEM GFX_EA_MAM_A3MEM GFX_EA_MAM_D3MEM GFX_EA_GMIWR_DATAMEM GFX_EA_DRAMWR_DATAMEM GFX_EA_IOWR_DATAMEM GFX_EA_GMIRD_CMDMEM GFX_EA_DRAMRD_CMDMEM GFX_EA_IORD_CMDMEM GFX_EA_GMIWR_CMDMEM GFX_EA_DRAMWR_CMDMEM GFX_EA_IOWR_CMDMEM GFX_EA_GMIRD_PAGEMEM GFX_EA_DRAMRD_PAGEMEM GFX_EA_GMIWR_PAGEMEM GFX_EA_DRAMWR_PAGEMEM GFX_EA_MAM_AFMEM GFX_EA_RRET_TAGMEM GFX_EA_WRET_TAGMEM GFX_SPI_WB_GRANT_30_MEM UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM GFX_GDS_OA_PIPE_MEM GFX_GDS_OA_PHY_DATA_RAM_MEM GFX_GDS_OA_PHY_CMD_RAM_MEM GFX_SPI_GDS_EXPREQ_MEM GFX_SPI_SR_MEM GFX_GDS_MEM GFX_SPI_LIFE_CNT_MEM GFX_TCC_WRITE_RETURN GFX_TA_FS_CFIFO GFX_TA_FS_DFIFO GFX_SQC_DATA_CU0_UTCL1_LFIFO GFX_SQC_DATA_CU1_UTCL1_LFIFO GFX_SQC_DATA_CU2_UTCL1_LFIFO GFX_SQC_DATA_CU3_UTCL1_LFIFO GFX_SQC_INST_UTCL1_LFIFO GFX_TA_FL_LFIFO GFX_TA_FX_LFIFO GFX_TCC_UC_ATOMIC_FIFO GFX_TCC_SRC_FIFO GFX_TCP_CMD_FIFO GFX_TCC_CACHE_TAG_PROBE_FIFO GFX_TCA_HOLE_FIFO UTC_VML2_RDIF_LOG_FIFO GFX_TCP_VM_FIFO GFX_TCA_REQ_FIFO GFX_TD_CS_FIFO GFX_SQC_BANKA_INST_UTCL1_MISS_FIFO GFX_SQC_BANKB_INST_UTCL1_MISS_FIFO GFX_SQC_BANKA_DATA_MISS_FIFO GFX_SQC_BANKB_DATA_MISS_FIFO GFX_SQC_BANKA_INST_MISS_FIFO GFX_SQC_BANKB_INST_MISS_FIFO GFX_SQC_BANKA_DATA_HIT_FIFO GFX_SQC_BANKB_DATA_HIT_FIFO GFX_TCC_LATENCY_FIFO GFX_TA_FS_AFIFO_LO GFX_TD_SS_FIFO_LO UTC_VML2_QUEUE_REQ GFX_CPF_ME1_ROQ GFX_CPF_ME2_ROQ GFX_TCC_IN_USE_TRANSFER UTC_VML2_WALKER UTCL2_ROUTER GFX_SQ_SGPR GFX_SQ_VGPR GFX_TCC_OUTPUT_FIFOS UTC_VML2_RDIF_ARADDRS UTC_VML2_QUEUE_RET Invoked command: ENABLE FEATURES Invoked command: DISABLE FEATURES Invoke completed with RAS TA status = 0x%X GFX_TCC_CACHE_DATA GFX_SPI_WB_GRANT_61_MEM GFX_TA_FS_AFIFO pcs_ras_inject_dataloss_error_mi200 pcs_ras_inject_reply_buf_underflow_error_mi200 pcs_ras_inject_elastic_buf_overflow_error_mi200 pcs_ras_inject_reply_buf_overflow_error_mi200 p@ @ >@ @ f@ v@ @ @ @ @ @ @ *@ @ R@ @ @ @ @ b@ P@ W@ v@
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