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CAL_STATUS /PROTECT_LITE_VAR_ARRAY_IMPEDANCE_MEASURE_STATUS € L CAL_R 5PROTECT_LITE_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION € P CAL_SET_STATUS 3PROTECT_LITE_VAR_ARRAY_IMPEDANCE_THRESH_CALC_STATUS L CAL_R_SELECTED -PROTECT_LITE_VAR_ARRAY_INITIAL_CALI_IMPEDANCE L TEMP_COIL_RATE /PROTECT_LITE_VAR_ARRAY_RATE_OF_COIL_TEMP_CHANGE € H TEMP_EST_COR )PROTECT_LITE_VAR_ARRAY_TEMP_EST_CORRECTED €
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TEMP_COIL_EST $PROTECT_LITE_VAR_ARRAY_TEMP_COIL_EST B T CAL_AMBIENT9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_AMBIENT_TEMPERATURE € C D DIAG_F0,PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F0 D X DIAG_F0_STATUS 9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_ANALYSIS_STATUS F d CAL_IMP_MEAS_CAL @PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION G D CAL_R_OUT +PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_R_OUT K T DIAG_Z_LOW_DIFF6PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_DIAGNOSTICS_LOW_DIFF L L CAL_RE_EST_GAIN-PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_RE_EST_GAIN M P
CAL_ALPHA_REF 1PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_ALPHA_REFERENCE N H
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M_DRC1_OP_LVL #MBDRC_DRC_1_STRUCT_DRC_OUTPUT_LEVEL € T T M_DRC2_LD_OP_LVL 0MBDRC_DRC_2_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL € t @
M_DRC2_OP_LVL #MBDRC_DRC_2_STRUCT_DRC_OUTPUT_LEVEL € y T M_DRC3_LD_OP_LVL 0MBDRC_DRC_3_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL € ™ @
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IC_H_XO_EN JINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE € / h IC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL € ò\ ò ACTISONIC Š < ACTISONIC_ENABLE ACTISONIC_ACTISONIC_ENABLE € ò ò LIMITER T LI_DRC_LD_OP_LVL 2LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL € ! D
LI_DRC_OP_LVL %LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL € & D LI_ENABLE *LIMITER_LIMITER_CTRL_STRUCT_LIMITER_ENABLE € ò0 ò
INPUT_ENHANCE \ IE_DRC_LD_OP_LVL 8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL € & H
IE_DRC_OP_LVL +INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL € + X IE_ENABLE 8 TG23_TONE_DIVIDE SDCA_TG23_TONE_DIVIDER ^ @ XU22_FDL_MES_OFF SDCA_XU22_FDL_MESSAGE_OFFSET € ` @ XU22_FDL_MES_LEN SDCA_XU22_FDL_MESSAGE_LENGTH € ò )ò WRITE_DETECT ò¤ #ò EVENT_LOGGER < EVLOG_HEADER EVENT_LOGGER_EVENT_LOG_HEADER € 0 EVLOG_EN EVENT_LOGGER_ENABLED € 8
BUFFER_STATUS EVENT_LOGGER_BUFFER_STATUS € @ EVLOG_ST_OFF EVENT_LOGGER_START_STREAM_OFFSET € 8 WAS_DISABLED EVENT_LOGGER_WAS_DISABLED €
< EVLOG_TS_SHIFT EVENT_LOGGER_TIMESTAMP_SHIFT € òX *ò ASP_MIXER 8 ASP_MIX_ENABLE ASP_MIXER_ASP_MIX_ENABLE € ò\ B SHORT_DETECT 8 SHORT_DETECTED SHORT_DETECT_SHORT_DETECTED € òÔ 3ò VMON_SYNTHESIS , ENABLE VMON_SYNTHESIS_ENABLE † P VMS_AC_MOD_IMAX3VMON_SYNTHESIS_ANALOG_CLIPPING_MODULATION_INDEX_MAX ‡ P VMS_AC_INT_R 0VMON_SYNTHESIS_ANALOG_CLIPPING_INTERNAL_RESISTOR ˆ P VMS_AC_EXT_R 0VMON_SYNTHESIS_ANALOG_CLIPPING_EXTERNAL_RESISTOR ‰ L
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DSP_BEEP_FREQ BOOT_BEEP_DSP_BEEP_FREQ € 8 DSP_BEEP_LEVEL BOOT_BEEP_DSP_BEEP_LEVEL € 8 BB_DSP_BEEP_DURBOOT_BEEP_DSP_BEEP_DURATION € 8 GPIO_BEEP_FREQ BOOT_BEEP_GPIO_BEEP_FREQ € 8 GPIO_BEEP_LEVELBOOT_BEEP_GPIO_BEEP_LEVEL € 4 BEEP_PENDING BOOT_BEEP_BEEP_PENDING € ò 1ò
TWEETER_XOVER ò8 0ò TWEETER_LIMITER \ TLI_DRC_LD_OP_LV :TWEETER_LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL € ! L TLI_DRC_OP_LVL -TWEETER_LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL € & \
TLI_ENABLE BTWEETER_LIMITER_TWEETER_LIMITER_CTRL_STRUCT_TWEETER_LIMITER_ENABLE € ò 5ò TWEETER_ENHANCE ò< 7ò SWDE H ( SWDE_ENSWDE_SWDE_ENABLE ,
SWDE_SW_EN SWDE_SWDE_SW_ENABLE ,
SWDE_DE_EN SWDE_SWDE_DE_ENABLE 8 SWDE_SW_M_F1_B0SWDE_ST_WIDE_MID_FILT_1_B0 8 SWDE_SW_M_F1_B1SWDE_ST_WIDE_MID_FILT_1_B1 8 SWDE_SW_M_F1_B2SWDE_ST_WIDE_MID_FILT_1_B2 < SWDE_SW_M_F1_MA1 SWDE_ST_WIDE_MID_FILT_1_MA1 < SWDE_SW_M_F1_MA2 SWDE_ST_WIDE_MID_FILT_1_MA2 8 SWDE_SW_M_F2_B0SWDE_ST_WIDE_MID_FILT_2_B0 8 SWDE_SW_M_F2_B1SWDE_ST_WIDE_MID_FILT_2_B1
8 SWDE_SW_M_F2_B2SWDE_ST_WIDE_MID_FILT_2_B2 < SWDE_SW_M_F2_MA1 SWDE_ST_WIDE_MID_FILT_2_MA1 < SWDE_SW_M_F2_MA2 SWDE_ST_WIDE_MID_FILT_2_MA2
8 SWDE_SW_M_F3_B0SWDE_ST_WIDE_MID_FILT_3_B0 8 SWDE_SW_M_F3_B1SWDE_ST_WIDE_MID_FILT_3_B1 8 SWDE_SW_M_F3_B2SWDE_ST_WIDE_MID_FILT_3_B2 < SWDE_SW_M_F3_MA1 SWDE_ST_WIDE_MID_FILT_3_MA1 < SWDE_SW_M_F3_MA2 SWDE_ST_WIDE_MID_FILT_3_MA2 8 SWDE_SW_S_F1_B0SWDE_ST_WIDE_SIDE_FILT_1_B0 8 SWDE_SW_S_F1_B1SWDE_ST_WIDE_SIDE_FILT_1_B1 8 SWDE_SW_S_F1_B2SWDE_ST_WIDE_SIDE_FILT_1_B2 @ SWDE_SW_S_F1_MA1 SWDE_ST_WIDE_SIDE_FILT_1_MA1 @ SWDE_SW_S_F1_MA2 SWDE_ST_WIDE_SIDE_FILT_1_MA2 8 SWDE_SW_S_F2_B0SWDE_ST_WIDE_SIDE_FILT_2_B0 8 SWDE_SW_S_F2_B1SWDE_ST_WIDE_SIDE_FILT_2_B1 8 SWDE_SW_S_F2_B2SWDE_ST_WIDE_SIDE_FILT_2_B2 @ SWDE_SW_S_F2_MA1 SWDE_ST_WIDE_SIDE_FILT_2_MA1 @ SWDE_SW_S_F2_MA2 SWDE_ST_WIDE_SIDE_FILT_2_MA2 8 SWDE_SW_S_F3_B0SWDE_ST_WIDE_SIDE_FILT_3_B0 8 SWDE_SW_S_F3_B1SWDE_ST_WIDE_SIDE_FILT_3_B1 8 SWDE_SW_S_F3_B2SWDE_ST_WIDE_SIDE_FILT_3_B2 @ SWDE_SW_S_F3_MA1 SWDE_ST_WIDE_SIDE_FILT_3_MA1 @ SWDE_SW_S_F3_MA2 SWDE_ST_WIDE_SIDE_FILT_3_MA2 ! 4 SWDE_SW_M_SCALESWDE_ST_WIDE_MID_SCALE " 4 SWDE_SW_M_SHIFTSWDE_ST_WIDE_MID_SHIFT # 4 SWDE_SW_S_SCALESWDE_ST_WIDE_SIDE_SCALE $ 4 SWDE_SW_S_SHIFTSWDE_ST_WIDE_SIDE_SHIFT % 8 SWDE_DE_M_F1_B0SWDE_D_ENH_MID_FILT_1_B0 & 8 SWDE_DE_M_F1_B1SWDE_D_ENH_MID_FILT_1_B1 ' 8 SWDE_DE_M_F1_B2SWDE_D_ENH_MID_FILT_1_B2 ( < SWDE_DE_M_F1_MA1 SWDE_D_ENH_MID_FILT_1_MA1 ) < SWDE_DE_M_F1_MA2 SWDE_D_ENH_MID_FILT_1_MA2 * 8 SWDE_DE_M_F2_B0SWDE_D_ENH_MID_FILT_2_B0 + 8 SWDE_DE_M_F2_B1SWDE_D_ENH_MID_FILT_2_B1 , 8 SWDE_DE_M_F2_B2SWDE_D_ENH_MID_FILT_2_B2 - < SWDE_DE_M_F2_MA1 SWDE_D_ENH_MID_FILT_2_MA1 . < SWDE_DE_M_F2_MA2 SWDE_D_ENH_MID_FILT_2_MA2 / 8 SWDE_DE_M_F3_B0SWDE_D_ENH_MID_FILT_3_B0 0 8 SWDE_DE_M_F3_B1SWDE_D_ENH_MID_FILT_3_B1 1 8 SWDE_DE_M_F3_B2SWDE_D_ENH_MID_FILT_3_B2 2 < SWDE_DE_M_F3_MA1 SWDE_D_ENH_MID_FILT_3_MA1 3 < SWDE_DE_M_F3_MA2 SWDE_D_ENH_MID_FILT_3_MA2 4 8 SWDE_DE_S_F1_B0SWDE_D_ENH_SIDE_FILT_1_B0 5 8 SWDE_DE_S_F1_B1SWDE_D_ENH_SIDE_FILT_1_B1 6 8 SWDE_DE_S_F1_B2SWDE_D_ENH_SIDE_FILT_1_B2 7 < SWDE_DE_S_F1_MA1 SWDE_D_ENH_SIDE_FILT_1_MA1 8 < SWDE_DE_S_F1_MA2 SWDE_D_ENH_SIDE_FILT_1_MA2 9 8 SWDE_DE_S_F2_B0SWDE_D_ENH_SIDE_FILT_2_B0 : 8 SWDE_DE_S_F2_B1SWDE_D_ENH_SIDE_FILT_2_B1 ; 8 SWDE_DE_S_F2_B2SWDE_D_ENH_SIDE_FILT_2_B2 < < SWDE_DE_S_F2_MA1 SWDE_D_ENH_SIDE_FILT_2_MA1 = < SWDE_DE_S_F2_MA2 SWDE_D_ENH_SIDE_FILT_2_MA2 > 8 SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0 ? 8 SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1 @ 8 SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2 A < SWDE_DE_S_v3_MA1 SWDE_D_ENH_SIDE_FILT_3_MA1 B < SWDE_DE_S_F3_MA2 SWDE_D_ENH_SIDE_FILT_3_MA2 C 4 SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALE D 4 SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFT E 4 SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALE F 4 SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFT I 0 SWDE_XFADE_BAL SWDE_SWDE_BALANCE ò€ /ò SHARED_PATCHING_STRUCTURE P SPTCH_MD_SLW_FRM -SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES